Name
Title | ||
|---|---|---|
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs |
Abstract | ||
|---|---|---|
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains ... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSI.2018.2855972 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Inverters,Phase locked loops,Delays,Frequency modulation,Standards,Radio frequency,Calibration | Phase-locked loop,Digitally controlled oscillator,Capacitor,Phase noise,Electronic engineering,CMOS,Modulation,Frequency modulation,dBc,Optoelectronics,Mathematics | Journal |
Volume | Issue | ISSN |
65 | 11 | 1549-8328 |
Citations | PageRank | References |
2 | 0.48 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Feng-Wei Kuo | 1 | 44 | 5.46 |
| Masoud Babaie | 2 | 195 | 25.05 |
| Huan-Neng Chen | 3 | 47 | 5.38 |
| Lan-Chou Cho | 4 | 95 | 15.32 |
| Chewnpu Jou | 5 | 101 | 13.34 |
| Mark Chen | 6 | 2 | 2.85 |
| Robert Bogdan Staszewski | 7 | 536 | 93.76 |