Paper Info
Title
A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS
Abstract
High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master-slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master-slave comparators and proposed encoders, the sampling rate is up to 21.12 GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-mu m SiGe BiCMOS technology and it only occupies 1.05 mm x 1.46 mm chip area. With a power consumption of 1.831 W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15 GS/s.
Year
DOI
Venue
2019
10.1142/S0218126619501676
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Analog-to-digital converter,leakage current compensation,strict synchronization,tree-based clock networks,SiGe
Digital signal processing,BiCMOS,Optical communication,Computer science,Analog-to-digital converter,Electronic engineering,Distortion
Journal
Volume
Issue
ISSN
28
10.0
0218-1266
Citations 
PageRank 
References 
0
0.34
1
Authors
6
Name
Order
Citations
PageRank
Jiquan Li100.68
YingMei Chen2243.53
Pan Tang300.34
Zhen Zhang400.68
hui wang530.89
Hao Huang600.34