Name
Title | ||
|---|---|---|
Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design |
Abstract | ||
|---|---|---|
This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power e +/- ciency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the e +/- ciency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65 nm technology. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1142/S0218126619501974 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
High threshold,multi-threshold-voltage CMOS (MTCMOS),sleep transistor (ST),sleepy CMOS-sleepy stack (SC-SS),ultra-low-power,VLSI,W/L equivalency,variable threshold-voltage CMOS (VTCMOS) | Vlsi circuit design,Power efficient,Computer science,CMOS,Electronic engineering,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
28 | 12.0 | 0218-1266 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anjali Sharma | 1 | 0 | 0.34 |
| Harsh Sohal | 2 | 0 | 0.68 |
| Harsimran Jit Kaur | 3 | 0 | 0.34 |