Paper Info
Title
A 7T Security Oriented SRAM Bitcell
Abstract
Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel PA attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000 {\times }$ </tex-math></inline-formula> lower write energy standard deviation between write “1” and “0” operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other PA resistant SRAM cells.
Year
DOI
Venue
2019
10.1109/tcsii.2018.2886175
IEEE Transactions on Circuits and Systems Ii-express Briefs
Keywords
Field
DocType
SRAM cells,Correlation,Transistors,Energy dissipation,Power demand,Arrays
Power analysis,Electronic engineering,Static random-access memory,Energy reduction,Power demand,Sram cell,Transistor,Mathematics,Embedded system,Power consumption
Journal
Volume
Issue
ISSN
66
8
1549-7747
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Robert Giterman1409.55
Osnat Keren210620.19
Alexander Fish312321.24