Name
Title | ||
|---|---|---|
Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques |
Abstract | ||
|---|---|---|
System on chip (SoC) is a microchip which integrates many semiconductor devices into a single chip. The complete system that is integrated with many components and circuits has to be tested for its performance. At the same time, testing of SoC should not affect the final cost of the chip. The production cost of each and every chip can be reduced by minimizing the test time of each SoC. The testing time of each SoC can be minimized by using test scheduling techniques more efficiently and effectively. In this paper, artificial intelligence-based natural-inspired techniques such as ACO, MACO, ABC, bat and firefly algorithms are proposed to perform effective test scheduling, thereby reducing the total cost of the chip. The proposed algorithms are implemented on d695 and p22810 benchmark circuits for various values of TAM widths. The performance of the various algorithms was evaluated, and it is inferred that among the several algorithms used bat algorithm performs much better in reducing the overall testing time of SoC, and hence, the SoC cost is also reduced. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1007/s00521-019-04039-6 | NEURAL COMPUTING & APPLICATIONS |
Keywords | DocType | Volume |
Artificial intelligence,Test scheduling,Ant colony optimization,Artificial bee colony algorithm,Bat algorithm,Firefly algorithm | Journal | 32.0 |
Issue | ISSN | Citations |
SP9 | 0941-0643 | 3 |
PageRank | References | Authors |
0.47 | 31 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gokul Chandrasekaran | 1 | 5 | 0.86 |
| Sakthivel Periyasamy | 2 | 3 | 1.15 |
| Karthikeyan Panjappagounder Rajamanickam | 3 | 3 | 0.81 |