Paper Info
Title
Ant Lion Optimized Bufferless Routing in the Design of Low Power Application Specific Network on Chip
Abstract
Network on chip is widely restricted with power utilization and area occupation due to the usage of buffers. Hence, the design of bufferless architecture entirely eliminates such kind of limitations. However, conventional methodologies will not provide low-power design with enhanced features by means of operational frequency and area. This work introduces an optimization algorithm along with bufferless routing in chip design. Ant lion optimized (ALO) routing topology in bufferless router achieves very less power. Power dissipation of ALO-bufferless technique is evaluated with conventional topologies, such as spin, octagon and cliché. Xilinx ISE design suite 14.5 is used for the purpose of design and validation of the planned work, and it is compared with fault-tolerant deflection routing and hierarchical FTDR in terms of throughput and fault rate. ALO-based bufferless routing achieves operational frequency of 780.153 MHz with 0.413 mW power consumption; while ant lion optimized buffered routing achieves operational frequency of 426.995 MHz and 0.750 mW for speed and power, respectively.
Year
DOI
Venue
2020
10.1007/s00034-019-01065-6
Circuits, Systems, and Signal Processing
Keywords
Field
DocType
Application-specific network on chip (ASNoC), Bufferless router, Ant lion optimization, Deflection routing, Low power
Application specific,Dissipation,Control theory,Network on a chip,Network topology,Integrated circuit design,Deflection routing,Throughput,Router,Computer hardware,Mathematics
Journal
Volume
Issue
ISSN
39
2
0278-081X
Citations 
PageRank 
References 
1
0.35
10
Authors
3
Name
Order
Citations
PageRank
N. L. Venkataraman110.35
R. Kumar2248.02
P. Mohamed Shakeel3356.80