Paper Info
Title
Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems
Abstract
One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, high-performance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in high-performance embedded systems. Our approach leverages OS-transparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.
Year
DOI
Venue
2019
10.1109/RTAS.2019.00009
2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Keywords
Field
DocType
multi-core,memory,cache,hypervisor,invalidation,interference,high performance embedded
Virtualization,Memory hierarchy,Shared memory,Cache,Computer science,Deterministic memory,Hypervisor,Cache coloring,Multi-core processor,Embedded system,Distributed computing
Conference
ISSN
ISBN
Citations 
1545-3421
978-1-7281-0679-3
3
PageRank 
References 
Authors
0.39
18
6
Name
Order
Citations
PageRank
Tomasz Kloda130.39
Marco Solieri262.82
Renato Mancuso317313.27
Nicola Capodieci48216.13
Paolo Valente511110.59
Marko Bertogna6101056.16