Name
Abstract | ||
|---|---|---|
The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit ... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1049/iet-cdt.2018.5040 | IET Computers & Digital Techniques |
Keywords | Field | DocType |
clocks,combinational circuits,delay lines,integrated circuit design,integrated circuit testing,integrated circuit yield,logic gates,mathematical analysis,Monte Carlo methods | Ring oscillator,Monte Carlo method,Computer science,Parallel computing,Voltage,Combinational logic,Electronic engineering,Electronic circuit | Journal |
Volume | Issue | ISSN |
13 | 3 | 1751-8601 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Zhang | 1 | 6 | 2.54 |
| Ji Li | 2 | 97 | 10.87 |
| Huimei Cheng | 3 | 4 | 2.44 |
| Haipeng Zha | 4 | 8 | 1.15 |
| Jeff Draper | 5 | 298 | 26.31 |
| Peter A. Beerel | 6 | 480 | 56.38 |