Name
Title | ||
|---|---|---|
High-Performance Dsp Platform For Digital Hearing Aid Soc With Flexible Noise Estimation |
Abstract | ||
|---|---|---|
Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors' DSP design is 2.71 mm(2), and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1049/iet-cds.2018.5374 | IET CIRCUITS DEVICES & SYSTEMS |
Keywords | Field | DocType |
instruction sets, system-on-chip, hearing aids, digital signal processing chips, low-power electronics, integrated circuit noise, flexible electronics, integrated circuit design, flexible noise estimation, complex hearing aid algorithms, high-performance algorithms, noise handling, noise estimation algorithms, noise environment, high-performance DSP platform, digital hearing aid SoC, hearing impairment, high-performance digital signal processing platform, digital hearing aid system, application-specific instruction-set processor, ASIP, hardware accelerators, power 1, 3 mW, voltage 1, 0 V, frequency 8, 0 MHz, size 65, 0 nm | Digital signal processing,Application-specific instruction-set processor,System on a chip,Digital hearing aid,Hearing aid,Chip,Electronic engineering,Standard cell,Computer hardware,Mathematics,Clock rate | Journal |
Volume | Issue | ISSN |
13 | 5 | 1751-858X |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaeseok Kim | 1 | 1 | 0.37 |
| Minjoon Kim | 2 | 15 | 3.88 |
| Sangwon Kim | 3 | 1 | 0.37 |