Name
Abstract | ||
|---|---|---|
A NMOS type low-dropout (NMOS-LDO) voltage regulator with fast transient response is proposed in this paper. The NMOS-LDO is a dual-loop circuit whose inner loop can increase the regulating speed of the output voltage of the proposed LDO, and a NPN is adapted to move the dominate pole from the output point to the inner of the LDO chip without any miller capacitor or other on-chip compensated capacitor. In 0.35$mu$m CMOS process, the simulation results of the proposed LDO show that the rise time and fall time of LDO are about 2.11$mu$s and 4.26$mu$s for 10$mu$A ~ 10mA step change of load current. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/mwscas.2018.8623951 | international midwest symposium on circuits and systems |
Field | DocType | Citations |
Inner loop,Transient response,Capacitor,Fall time,NMOS logic,Computer science,Rise time,Electronic engineering,Electrical engineering,Low-dropout regulator,Voltage regulator | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ping Luo | 1 | 1 | 2.71 |
| Zelang Liu | 2 | 0 | 0.34 |
| Long Huang | 3 | 0 | 2.03 |
| Shaowei Zhen | 4 | 5 | 2.35 |