Paper Info
Title
Exploring Memory Persistency Models for GPUs
Abstract
Given its high integration density, high speed, byte addressability, and low standby power, non-volatile or persistent memory is expected to supplement/replace DRAM as main memory. Through persistency programming model (which defines durability ordering of stores) and durable transaction constructs, the programmer can provide recoverable data structure (RDS) which allows programs to recover to a consistent state after a failure. While persistency models have been well studied for CPUs, they have been neglected for graphics processing units (GPUs). Considering the importance of GPUs as a dominant accelerator for high performance computing, we investigate persistency models for GPUs. GPU applications exhibit substantial differences with CPUs applications, hence in this paper we adapt, re-architect, and optimize CPU persistency models for GPUs. We design a pragma-based compiler scheme for expressing persistency model for GPUs. We identify that the thread hierarchy in GPUs offers intuitive scopes to form epochs and durable transactions. We find that undo logging produces significant performance overheads. We propose to use idempotency analysis to reduce both logging frequency and the size of logs. Through both real-system and simulation evaluations, we show low overheads of our proposed architecture support.
Year
DOI
Venue
2019
10.1109/PACT.2019.00032
2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)
Keywords
Field
DocType
GPU,Memory Persistency
Data structure,Byte,Programmer,Undo,Programming paradigm,Supercomputer,Computer science,Parallel computing,Compiler,Addressability,Distributed computing
Journal
ISSN
ISBN
Citations 
1089-795X
978-1-7281-3614-1
0
PageRank 
References 
Authors
0.34
9
4
Name
Order
Citations
PageRank
Zhen Lin1354.21
Mohammad A. Alshboul2143.26
Yan Solihin32057111.56
Huiyang Zhou499463.26