Title
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification
Abstract
An inference system-on-chip (SoC) is designed to extract spatio-temporal features from videos for action classification. The SoC contains an inference core that implements a recurrent neural network in three processing layers. High sparsity is enforced in each layer of processing, reducing the complexity by two orders of magnitude and allowing multiply accumulates to be replaced by select accumulates. Spatio-temporal kernel and activation compression are applied to reduce memory by 43% and 64%, respectively. The design is demonstrated in a 2.53-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 40-nm CMOS chip with an OpenRISC core, providing control and classification. With the inference core extracting spatio-temporal features and a soft-max classifier programmed on the OpenRISC core, the SoC classifies KTH Human Action Data Set at a 76.7% accuracy. At 0.9 V and 250 MHz, the SoC achieves 1.70TOPS, dissipating 135 mW.
Year
DOI
Venue
2019
10.1109/jssc.2019.2907406
IEEE Journal of Solid-state Circuits
Keywords
Field
DocType
Feature extraction,Neurons,Complexity theory,Streaming media,Inference algorithms,Video sequences,Radio frequency
Kernel (linear algebra),Pattern recognition,OpenRISC,Inference,Computer science,Recurrent neural network,Electronic engineering,Radio frequency,Feature extraction,Artificial intelligence,Classifier (linguistics),Order of magnitude
Journal
Volume
Issue
ISSN
54
7
0018-9200
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
C C Chen1242.70
Ching-En Lee2215.86
Chester Liu301.01
Zhengya Zhang450248.41