Paper Info
Title
Design of an Optimized CMOS ELM Accelerator
Abstract
In the last decade, artificial intelligence (AI) has emerged at the forefront of driving many technological innovations. A variety of algorithms have been proposed as possible alternatives to implement AI in computing systems. Extreme learning machine (ELM) has emerged as one of the most effective training algorithms for simple applications based on single layer feed-forward neural networks (SLFN) because of its unique training method. Hardware implementation of neural network algorithms is a critical requirement for deploying them in timesensitive applications. In this paper, we present a simplified AI accelerator based on CMOS technology that implements an ELM based inference engine. We present analysis of implementing such an accelerator on different technology nodes with a comparative analysis to analyze the impact of technology node scaling on performance of the proposed accelerator in terms of power and area. For the analysis, the workload used was a network of dimensions 81x18x1. We observed a remarkable benefit in speed (1.3x), area (14x) and power (7x) by scaling the design from 180 nm to 45 nm. Further, we present an analysis showing benefits of introducing emerging non-volatile memory (NVM) technologies like RRAM as the primary memory technology for the accelerator. The analysis shows that replacing the conventional CMOS with RRAM would give significant benefits in leakage (4.5x) and area (33x).
Year
DOI
Venue
2019
10.1109/VLSID.2019.00094
2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
Keywords
Field
DocType
AI, Neural networks, Accelerator, Neuromorphic computing, ELM, NVM
Computer science,Electronic engineering,CMOS
Conference
ISSN
ISBN
Citations 
1063-9667
978-1-7281-0410-2
0
PageRank 
References 
Authors
0.34
8
4
Name
Order
Citations
PageRank
K. S. Manoj Kumar12810.34
Umesh Chandra Lohani200.34
vivek parmar385.42
manan suri4107.84