Name
Abstract | ||
|---|---|---|
This paper presents a current DAC based configurable wide output voltage range Low Drop-Out (LDO) regulator. This LDO uses a multi-supply operational amplifier architecture that uses low supply voltage (1.8V) for input stage in differential amplifier and high supply voltage (5V) for output stage. A nested miller compensation combined with buffer compensation scheme is presented that provides a fast transient response and full range AC stability from 0 to 100mA load current for an output capacitive load of 50pF using compensation capacitor of 5pF. LDO output is configurable using internal current based digital to analog converter (DAC) and output voltage ranges from 2.3V to 5.5V with a step of 107mV. Total loop gain of LDO is 127dB at DC and PSRR is -40dB at 1MHz frequency for no current load condition. Presented LDO is designed in 110nm STMicroelectronics BCD9s technology; consuming 30μA of total ground current (without current DAC). |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSID.2019.00073 | 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
BCD,LDO,DAC,Voltage Regulator,PSRR,Line Regulaton,Load Regulation | Computer science,Electronic engineering,Power supply rejection ratio | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-7281-0410-2 | 0 |
PageRank | References | Authors |
0.34 | 8 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vivek Tyagi | 1 | 0 | 1.35 |
| Vikas Rana | 2 | 5 | 4.87 |
| Laura Capecchi | 3 | 5 | 1.88 |
| Marcella Carissimi | 4 | 5 | 3.24 |
| Riccardo Zurla | 5 | 3 | 0.92 |
| Marco Pasotti | 6 | 0 | 1.01 |