Paper Info
Title
Efficient FPGA Implementation of Multilayer Perceptron for Real-Time Human Activity Classification.
Abstract
The smartphone-based human activity recognition (HAR) systems are not capable to deliver high-end performance for challenging applications. We propose a dedicated hardware-based HAR system for smart military wearables, which uses a multilayer perceptron (MLP) algorithm to perform activity classification. To achieve the flexible and efficient hardware design, the inherent MLP architecture with parallel computation is implemented on FPGA. The system performance has been evaluated using the UCI human activity dataset with 7767 feature samples of 20 subjects. The three combinations of a dataset are trained, validated, and tested on ten different MLP models with distinct topologies. The MLP design with the 7-6-5 topology is finalized from the classification accuracy and cross entropy performance. The five versions of the final MLP design (7-6-5) with different data precision are implemented on FPGA. The analysis shows that the MLP designed with 16-bit fixed-point data precision is the most efficient MLP implementation in the context of classification accuracy, resource utilization, and power consumption. The proposed MLP design requires only 270 ns for classification and consumes 120 mW of power. The recognition accuracy and hardware results performance achieved are better than many of the recently reported works.
Year
DOI
Venue
2019
10.1109/ACCESS.2019.2900084
IEEE ACCESS
Keywords
Field
DocType
Human activity recognition,multilayer perceptron,smart military wearables,classifier hardware implementation,field programmable gate array
Activity classification,Computer architecture,Computer science,Field-programmable gate array,Multilayer perceptron,Distributed computing
Journal
Volume
ISSN
Citations 
7
2169-3536
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Nikhil B. Gaikwad101.35
Varun Tiwari262.13
Avinash G. Keskar3127.41
N. C. Shivaprakash441.40