Name
Abstract | ||
|---|---|---|
A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation. However, it requires periodic refresh cycles to maintain its data which deteriorates due to leakage. The refresh-rate, which is traditionally set according to the worst cell in the array under extreme operating conditions, leads to a significant refresh power consumption and decreased memory availability. In this paper, we propose to reduce the cost of GC-eDRAM refresh by employing failure detection to lower the refresh-rate. A 4T dynamic complementary dual-modular redundancy bitcell is proposed to offer per-bit error detection, resulting in a substantial decrease in the refresh-rate and over 60% power reduction compared with the SRAM. The proposed approach is also compared with the conventional SRAM and GCeDRAM implementations with integrated error correction codes, demonstrating significant area and latency reductions. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ACCESS.2019.2901738 | IEEE ACCESS |
Keywords | Field | DocType |
Error detection and correction,error correcting codes,SRAM,gain cells,logic-compatible eDRAM,GC-eDRAM,low power | Computer science,Efficient energy use,Distributed computing | Journal |
Volume | ISSN | Citations |
7 | 2169-3536 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Giterman | 1 | 40 | 9.55 |
| Roman Golman | 2 | 0 | 2.03 |
| Adam Teman | 3 | 129 | 19.12 |