Paper Info
Title
An Enhanced Transfer Delay-Based Frequency Locked Loop for Three-Phase Systems With DC Offsets.
Abstract
In this paper, an enhanced transfer delay-based frequency locked loop (ETD-FLL) is proposed to estimate the frequency, the positive- and negative-sequence voltage with strong immunity against dc offsets. By analyzing the relationship between the grid voltage and its transfer delay signals, a linear regression model is established, which is related to the unknown parameters-the dc offsets and grid frequency. Accordingly, the problem of positive- and negative-sequence voltage detection is transformed as the issue of parameter identification based on the obtained model. Then, the normalized gradient method is proposed to estimate the unknown parameters in the established model and finally achieve the detection of positive- and negative-sequence voltage. A mathematic proof is provided to indicate that the proposed method has good steady-state accuracy and strong dc offset immunity. In addition, the proposed ETD-FLL has fast dynamics due to its transfer delay structure. The experimental results further confirm that the proposed method has good performance in terms of dynamics and dc offset immunity.
Year
DOI
Venue
2019
10.1109/ACCESS.2019.2903581
IEEE ACCESS
Keywords
Field
DocType
Transfer delay,frequency locked loop,three-phase grids,grid synchronization,dc offsets
Three phase system,Gradient method,Normalization (statistics),Frequency-locked loop,Computer science,Control theory,Voltage,DC bias,Frequency grid,Linear regression,Distributed computing
Journal
Volume
ISSN
Citations 
7
2169-3536
0
PageRank 
References 
Authors
0.34
0
5
Name
Order
Citations
PageRank
Zhiyong Dai101.01
Peiqi Zhao200.34
Xiaolei Chen321.06
Mingdi Fan421.79
Juxiang Zhang500.34