Name
Abstract | ||
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Historically, continuous improvements in general-purpose processors have fueled the economic success and growth of the IT industry. However, the diminishing benefits from transistor scaling and conventional optimization techniques necessitates moving beyond common practices. Approximate computing is one such unconventional technique that has shown promise in pushing the boundaries of general-purpose processing. This paper sets out to employ approximation for processors that are commonly used in cyber-physical domains and may become building blocks of Internet of Things. To this end, we propose AxMemo to exploit the computation redundancy that stems from data similarity in the inputs of code blocks. Such input behavior is prevalent in cyber-physical systems as they deal with real-world data that naturally harbors redundancy. Therefore, in contrast to existing memoization techniques that replace costly floating-point arithmetic operations with limited number of inputs, AxMemo focuses on memoizing blocks of code with potentially many inputs. As such, AxMemo aims to replace long sequences of instructions with a few hash and lookup operations. By reducing the number of dynamic instructions, AxMemo alleviates the von Neumann and execution overheads of passing instructions through the processor pipeline altogether. The challenge AxMemo facing is to provide low-cost hashing mechanisms that can generate rather unique signature for each multi-input combination. To address this challenge, we develop a novel use of Cyclic Redundancy Checking (CRC) to hash the inputs. To increase lookup table hit rate, AxMemo employs a two-level memoization lookup, which utilizes small dedicated SRAM and spare storage in the last level cache. These solutions enable AxMemo to efficiently memoize relatively large code regions with variable input sizes and types using the same underlying hardware. Our experiment shows that AxMemo offers 2.64× speedup and 2.58 × energy reduction with mere 0.2% of quality loss averaged across ten benchmarks. These benefits come with an area overhead of just 2.1%.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3307650.3322215 | Proceedings of the 46th International Symposium on Computer Architecture |
Keywords | Field | DocType |
approximate computing, hardware-software co-design, memoization | Lookup table,Computer science,Cyclic redundancy check,Cache,Parallel computing,Compiler,Redundancy (engineering),Hash function,Memoization,Computer hardware,Speedup | Conference |
ISSN | ISBN | Citations |
1063-6897 | 978-1-4503-6669-4 | 0 |
PageRank | References | Authors |
0.34 | 18 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenhong Liu | 1 | 101 | 12.87 |
| Amir Yazdanbakhsh | 2 | 241 | 15.28 |
| Dong Kai Wang | 3 | 4 | 0.72 |
| H. Esmaeilzadeh | 4 | 1443 | 69.71 |
| Nam Sung Kim | 5 | 3268 | 225.99 |