Name
Title | ||
|---|---|---|
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube |
Abstract | ||
|---|---|---|
Emerging 3D memory technologies, such as the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), provide increased bandwidth and massive memory-level parallelism. Efficiently integrating emerging memories into existing system pose new challenges and require detailed evaluation in a real computing environment. In this paper, we propose MEG, an open-source, configurable, cycle-exact, and RISC-V based full system simulation infrastructure using FPGA and HMC. MEG has three highly configurable design components: (i) a HMC adaptation module that not only enables communication between the HMC device and the processor cores but also can be extended to fit other memories (e.g., HBM, nonvolatile memory) with minimal effort, (ii) a reconfigurable memory controller along with its OS support that can be effectively leveraged by system designers to perform software-hardware co-optimization, and (iii) a performance monitor module that effectively improves the observability and debuggability of the system to guide performance optimization. We provide a prototype implementation of MEG on Xilinx VCU110 board and demonstrate its capability, fidelity, and flexibility on real-world benchmark applications. We hope that our open-source release of MEG fills a gap in the space of publicly-available FPGA-based full system simulation infrastructures specifically targeting memory system and inspires further collaborative software/hardware innovations. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/FCCM.2019.00029 | 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
Keywords | Field | DocType |
Bandwidth,Field programmable gate arrays,Optimization,Parallel processing,Monitoring,SDRAM | Computer architecture,Observability,Computer science,Hybrid Memory Cube,High Bandwidth Memory,Field-programmable gate array,Real-time computing,Non-volatile memory,Bandwidth (signal processing),Multi-core processor,Memory controller | Conference |
ISBN | Citations | PageRank |
978-1-7281-1131-5 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jialiang Zhang | 1 | 94 | 11.46 |
| Yang Liu | 2 | 0 | 0.34 |
| Gaurav Jain | 3 | 30 | 6.08 |
| Yue Zha | 4 | 26 | 6.73 |
| Jonathan Ta | 5 | 0 | 0.34 |
| Jing Li | 6 | 208 | 30.49 |