Name
Abstract | ||
|---|---|---|
A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dual-modular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1587/elex.16.20190208 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
latch, N-hit, P-hit, single event upset | Computer science,Electronic engineering,Single event upset,Electrical engineering | Journal |
Volume | Issue | ISSN |
16 | 11 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Changyong Liu | 1 | 11 | 2.79 |
| Nianlong Liu | 2 | 0 | 0.34 |
| Zhiting Lin | 3 | 29 | 8.47 |
| Xiulong Wu | 4 | 17 | 5.82 |
| Chunyu Peng | 5 | 30 | 10.29 |
| Qiang Zhao | 6 | 1 | 3.39 |
| Xuan Li | 7 | 124 | 27.25 |
| Junning Chen | 8 | 3 | 1.11 |
| Xuan Zeng | 9 | 408 | 75.96 |
| Xiang-Dong Hu | 10 | 3 | 3.09 |