Paper Info
Title
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design
Abstract
Considering the insatiable demand for high-performance computing, on-chip cache capacity increases rapidly. Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) is a promising cache candidate due to ultralow standby power, high-access speed, and integration density. Unfortunately, when the feature size of magnetic tunnel junction (MTJ) scales down to 1 Xnm, read current approaches write current closely, which may result in read disturbance threatening the reliability of STT-MRAM. Furthermore, the elevating on-chip temperature reduces the thermal stability of STT-MRAM remarkably and aggravates the read disturbance. Error correction code (ECC) is an effective technique to enhance memory reliability. In this paper, we take advantage of the thermal dependence of STT-MRAM and propose a thermally adaptive ECC design, called “Chameleon,” that can adjust the ECC protection strength dynamically to reduce the ECC storage overhead and improve the cache access performance and energy efficiency. Experimental results show that compared to the conservative nonadaptive ECC scheme, our design can improve both cache performance and energy consumption effectively.
Year
DOI
Venue
2019
10.1109/tvlsi.2019.2913207
IEEE Transactions on Very Large Scale Integration Systems
Keywords
Field
DocType
Error correction codes,Magnetic tunneling,System-on-chip,Thermal stability,Reliability engineering,Temperature sensors
System on a chip,Standby power,Computer science,Efficient energy use,Cache,Electronic engineering,Error detection and correction,Magnetoresistive random-access memory,Tunnel magnetoresistance,Energy consumption,Embedded system
Journal
Volume
Issue
ISSN
27
8
1063-8210
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
Bi Wu1176.61
Beibei Zhang2195.58
Yuan-Qing Cheng3338.77
Ying Wang427655.61
Dijun Liu5103.96
Weisheng Zhao6730105.43