Name
Title | ||
|---|---|---|
Improving on State Register Identification in Sequential Hardware Reverse Engineering |
Abstract | ||
|---|---|---|
In the past years, new hardware reverse engineering methods for sequential gate-level netlists have been developed to detect Hardware Trojans and counteract Design Piracy. A critical part of sequential gate-level netlist reverse engineering is the identification of state registers. A promising method to solve this problem, RELIC, proposed by T. Meade et al., is based on input structure similarities of registers to differentiate between state and non-state registers. We propose an improvement to this method, fastRELIC: it outperforms RELIC in terms of speed and computational complexity. A complexity analysis shows the upper bound of O(R
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
) (R: # registers) for both methods, but a linear lower bound Ω(R) for fastRELIC. Empirical results with fastRELIC provide a speedup of up to 100×. This allowed us to analyze real-life designs with more than 4,000 registers and 50,000 gates. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/HST.2019.8740844 | 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
Keywords | Field | DocType |
Hardware Reverse Engineering,Sequential Reverse Engineering,State Register Identification,FSM Extraction | Netlist,Logic gate,Computer science,Upper and lower bounds,Reverse engineering,Computer hardware,Computational complexity theory,Speedup | Conference |
ISBN | Citations | PageRank |
978-1-5386-8065-0 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michaela Brunner | 1 | 0 | 0.68 |
| Johanna Baehr | 2 | 0 | 0.34 |
| Georg Sigl | 3 | 447 | 62.13 |