Name
Abstract | ||
|---|---|---|
This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSI-DAT.2019.8741927 | 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | Field | DocType |
algorithmic multiported memory,memory design,remap table,write addresses,fit algorithm,pipeline scheme,banking structure,SRAM cells,registers,hash write controller | Most significant bit,Control theory,Computer science,Latency (engineering),Algorithm,Static random-access memory,Porting,Hash function,Throughput | Conference |
ISSN | ISBN | Citations |
2380-7369 | 978-1-7281-0656-4 | 0 |
PageRank | References | Authors |
0.34 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bo-Ya Chen | 1 | 0 | 0.68 |
| Bo-En Cher | 2 | 0 | 0.34 |
| Bo-Cheng Lai | 3 | 0 | 0.34 |