Paper Info
Title
A 2.4-Mm(2) 130-Mw Mmse-Nonbinary Ldpc Iterative Detector Decoder For 4 X 4 256-Qam Mimo In 65-Nm Cmos
Abstract
Iterative detection and decoding (IDD) employs a soft-in soft-out (SISO) detector and an SISO forward error correction (FEC) decoder in an iterative loop to improve the receiver performance in multiple-input multiple-output (MIMO) wireless communications. This paper describes a 256-QAM 4 x 4 prototype IDD design made up of a minimum mean square error (MMSE) detector and a nonbinary low-density parity-check (NBLDPC) decoder with the symbol size of the NBLDPC code matched to the modulation to enhance performance. By directly translating between nonbinary symbols and constellation points, the detector-decoder interface is simplified. We present a Gb/s MMSE detector using a shortened tandem scheduling, a low-latency dual-lookup reciprocal unit, an optimized interleaved microarchitecture, and a Gb/s NBLDPC decoder with efficient internal skipping paths and memory allocation. The designs were demonstrated in a 0.7-mm(2) 1.38-Gb/s MMSE detector and a 1.7-mm(2) 1.02-Gb/s-NBLDPC decoder that are integrated in a 65-nm CMOS test chip. The chip is measured to achieve 19.2 pJ/b in detection and 20.1 pJ/b/iteration in decoding.
Year
DOI
Venue
2019
10.1109/JSSC.2019.2904876
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords
DocType
Volume
Iterative detection and decoding (IDD), minimum mean square error (MMSE) detector, multiple-input multiple-output (MIMO) processor, nonbinary low-density parity-check (NBLDPC) decoder
Journal
54
Issue
ISSN
Citations 
7
0018-9200
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Wei Tang1121.37
Chia-Hsiang Chen2164.68
Zhengya Zhang350248.41