Name
Abstract | ||
|---|---|---|
In active noise control (ANC) systems the filtered-x least mean squares (FxLMS) algorithm is the most widely used reduction algorithm. The feedback FxLMS can operate without an external reference signal but has the disadvantage of being very sensitive to delays in the secondary path. As the processing latency of the FxLMS itself adds to the secondary path delay, it is critical to minimize the processing latency. Large-scale ANC systems benefit from high order filters and high sample rates. This combination is very computational demanding. Specific hardware implementations can achieve more complex filter configurations compared to software implementations on general purpose processors, but are less flexible to changes.
This paper presents a parameterizable hardware design implemented in very-high-speed integrated circuit hardware description language (VHDL) that can operate at different bit widths and can be configured to optimize for high sample rates, long filter lengths or low hardware resource usage. The design is able to provide a constant processing latency of only 3 clock cycles that is independent from the filter length.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3337801.3337802 | Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies |
Keywords | DocType | ISBN |
FPGA, Feedback FxLMS, Hardware Design, VHDL | Conference | 978-1-4503-7255-8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexander Klemd | 1 | 0 | 0.34 |
| Marcel Eckert | 2 | 3 | 2.55 |
| Bernd Klauer | 3 | 50 | 14.36 |
| Jonas Hanselka | 4 | 0 | 0.34 |
| JDelf Sachau | 5 | 0 | 0.34 |