Name
Abstract | ||
|---|---|---|
During scan shift, high simultaneous toggling of sequential logic on a System-on-Chip (SoC) can result in increased Power Supply Noise (PSN). The problem gets exacerbated when the switching logic is present in neighboring blocks on the SoC that share the same power rails. To solve this voltage noise problem, we propose a new graph coloring algorithm that assigns staggered shift-clocks to the SoC blocks such that (i) no two neighboring blocks use the same shift-clock (to reduce local hotspots), and (ii) the number of scan cells toggling per shift clock is equalized (to reduce global noise). The new algorithm takes into account the total number of scan flops per block, and the assignment of stagger clocks is done such that the total number of scan flops that toggle per staggered shift-clock is balanced at the power rail-level. Using silicon data from NVIDIA's recently taped-out chips, we show that the stagger assignment using our new algorithm results in at 70% PSN reduction compared to conventional scan shift and around 21% PSN reduction compared to the previously proposed stagger assignment solutions. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VTS.2019.8758676 | 2019 IEEE 37th VLSI Test Symposium (VTS) |
Keywords | Field | DocType |
low-power scan shift,sequential logic,voltage noise problem,graph coloring algorithm,stagger clocks,system-on-chip,graph coloring based solution,power supply noise,local hotspots,scan flops per block,taped-out chips | Voltage noise,Sequential logic,FLOPS,Computer science,Algorithm,Electronic engineering,Graph coloring | Conference |
ISSN | ISBN | Citations |
1093-0167 | 978-1-7281-1171-1 | 0 |
PageRank | References | Authors |
0.34 | 17 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Saurabh Gupta | 1 | 0 | 0.34 |
| Bonita Bhaskaran | 2 | 6 | 1.89 |
| Shantanu Sarangi | 3 | 2 | 1.59 |
| Ayub Abdollahian | 4 | 8 | 1.32 |
| Jennifer Dworak | 5 | 28 | 5.50 |