Name
Abstract | ||
|---|---|---|
Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient. We propose and automate a method to synthesize ternary logic circuits. Our design of ternary logic circuits is based on static gate design, and exploits carbon nanotube field-effect transistors. We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power-delay product by 52.72 % over the state-of-the-art method for a ternary half adder, and by 68.06 % for a ternary multiplier. We also have improved power-delay product by 37.30 % over the state-of-the-art method for a ternary full adder that has high load capacitance. Our design has an average of 42.43 % fewer transistors than the existing design for circuits that have large number of inputs. As circuits become larger, the improved power-delay product and reduced transistor count are advantageous. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ISMVL.2019.00035 | 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) |
Keywords | Field | DocType |
Multi-valued logic,Ternary logic circuits,Synthesis methodology,Quine-McCluskey algorithm,CNTFET | Transistor count,Logic synthesis,Logic gate,Adder,Computer science,Electronic engineering,Ternary operation,Quine–McCluskey algorithm,Transistor,Electronic circuit | Conference |
ISSN | ISBN | Citations |
0195-623X | 978-1-7281-0093-7 | 0 |
PageRank | References | Authors |
0.34 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sung Yun Lee | 1 | 0 | 0.34 |
| Sunmean Kim | 2 | 1 | 2.37 |
| Seokhyeong Kang | 3 | 388 | 32.89 |