Title | ||
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4-Channel Front-End Integrated Circuit For Readout of Large Area of SiPM under Liquid Argon |
Abstract | ||
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This paper presents the structure and transistor-level design of CMOS front-end amplifier for the readout of large area SiPM at LAr temperature (87 K). The front-end circuit, a transimpedance amplifier and a summing amplifier, has been designed using a standard 110 nm CMOS technology, and the simulation results with the foundry PDK are included in this work. Each stage is implemented in a Folded Cascode Operational Transimpedance Amplifier (OTA) architecture with a power rail of +1.25 V and -1.25 V, a power consumption of 95 mW and an open-loop gain over 100 dB. The target sensor is a SiPM tile of 24 cm
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produced in the Darkside collaboration project, with 6 M of quenching resistance and 6 nF/cm
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capacitance. For a single photoelectron (250 fC), the front-end can achieve a signal-noise ratio above 12 and a jitter better than 45 ns. |
Year | DOI | Venue |
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2019 | 10.1109/PRIME.2019.8787758 | 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) |
Keywords | Field | DocType |
transistor-level design,readout,LAr temperature,summing amplifier,foundry PDK,Folded Cascode Operational Transimpedance Amplifier architecture,power rail,power consumption,open-loop gain,SiPM tile,4-channel front-end integrated circuit,liquid argon,front-end amplifier,large area SiPM,standard CMOS technology,darkside collaboration project,quenching resistance,structure design,voltage -1.25 V,temperature 87.0 K,size 110.0 nm,voltage 1.25 V,power 95.0 mW | Cascode,Computer science,Electronic engineering,CMOS,Transimpedance amplifier,Silicon photomultiplier,Operational amplifier applications,Transistor,Integrated circuit,Optoelectronics,Amplifier | Conference |
ISBN | Citations | PageRank |
978-1-7281-3550-2 | 0 | 0.34 |
References | Authors | |
0 | 1 |
Name | Order | Citations | PageRank |
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Alejandro D. Martinez R. | 1 | 0 | 0.34 |