Name
Abstract | ||
|---|---|---|
This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTJs (DMTJs) as comparatively evaluated with respect to conventional solution based on single-barrier MTJs (SMTJs). The comparative study was carried out at different design abstraction levels: (i) a bitcell-Ievel analysis relying on the use of Verilog-A compact models, and (ii) an architecture-level analysis for various memory sizes. Overall, our simulation results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow reducing write latency of about 60% than their SMTJ-based counterparts. This is achieved while assuring lower energy consumption under both write (-40%) and read (-27%) accesses, at the cost of reduced sensing margins. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/SMACD.2019.8795223 | 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) |
Keywords | Field | DocType |
Double-barrier magnetic tunnel junction (DMTJ),STT-MRAM,FinFET,technology-voltage scaling | Latency (engineering),Efficient energy use,Computer science,Electronic engineering,Magnetoresistive random-access memory,Energy consumption | Conference |
ISSN | ISBN | Citations |
2575-4874 | 978-1-7281-1202-2 | 2 |
PageRank | References | Authors |
0.44 | 5 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Esteban Garzon | 1 | 5 | 2.63 |
| Raffaele De Rose | 2 | 57 | 10.63 |
| Felice Crupi | 3 | 25 | 8.33 |
| Lionel Trojman | 4 | 2 | 0.44 |
| Giovanni Finocchio | 5 | 9 | 1.15 |
| Mario Carpentieri | 6 | 14 | 3.47 |
| Marco Lanuzza | 7 | 203 | 28.64 |