Name
Abstract | ||
|---|---|---|
The challenge addressed in this paper consists in offloading packet-based pacing to a hardware Network Interface Card, while retaining the flexibility of software timers. In this direction, we propose, design, implement, and evaluate a hardware calendar, which can be programmed via a simple yet very flexible programming interface leveraging stateful (adaptive) per-packet timers. We show, for both specific examples (exponential, linearly increasing, etc) as well as for the general case, how to derive such a per-packet timer setting from a high-level desired rate envelope. Further, we describe and evaluate an FPGA implementation which relies on a novel insertion strategy for solving collisions in the calendar's hash table. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/HPSR.2018.8850731 | 2018 IEEE 19th International Conference on High Performance Switching and Routing (HPSR) |
Keywords | Field | DocType |
programmable hardware calendar,high-level desired rate envelope,FPGA implementation,flexible programming interface,hardware network interface card,high resolution pacing,per-packet timer setting,hash table | Computer science,Network packet,Field-programmable gate array,Software,Stateful firewall,Timer,Computer hardware,Network interface controller,Hash table | Conference |
ISSN | ISBN | Citations |
2325-5595 | 978-1-5386-7802-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Salvatore Pontarelli | 1 | 368 | 54.05 |
| Giuseppe Bianchi | 2 | 1009 | 84.46 |
| Michael Welzl | 3 | 51 | 8.40 |