Paper Info
Title
FPGA Implementation of IFFT Architecture with Enhanced Pruning Algorithm for Low Power Application
Abstract
The improved architecture of IFFT is developed and presented in this paper. Number of arithmetic operation is more in the normal working of conventional Inverse Fast Fourier Transform. An enhanced pruning algorithm is utilized to reduce the number of arithmetic operations in the IFFT architecture. The performance of the improved IFFT architecture is estimated to find its suitability for the low power Wireless communication system. It is implemented in 8-point IFFT architecture using decimation in frequency algorithm using hardware description language. It is implemented in XC7z020clg484-1 from Zynq-7000 family with a frequency of 220 MHz. It is found that the improved IFFT architecture reduces maximum of 40% of the arithmetic operations, which reduces the power consumption by maximum of 10%. Hence the improved IFFT architecture can be used in the signal processing units in wireless application.
Year
DOI
Venue
2019
10.1016/j.micpro.2019.06.010
Microprocessors and Microsystems
Keywords
Field
DocType
Enhanced pruned algorithm (EPA),Field-programmable gate array (FPGA),Orthogonal frequency division multiplexing (OFDM),Quadrature amplitude modulation (QAM),Filter-bank multi-carrier with offset quadrature amplitude modulation (FBMC/OQAM),Inverse Fast Fourier Transform (IFFT)
Pruning algorithm,Signal processing,Architecture,Wireless,Computer science,Parallel computing,Field-programmable gate array,Fast Fourier transform,Computer hardware,Hardware description language,Power consumption
Journal
Volume
ISSN
Citations 
71
0141-9331
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Abraham Chavacheril Geevarghese100.34
M. Madheswaran210215.57