Name
Title | ||
|---|---|---|
Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support |
Abstract | ||
|---|---|---|
A system's memory size is often dictated by worst-case workloads with highest memory requirements; this causes memory to be underutilized in the common case when the system is not running its worst-case workloads. Cognizant of this memory underutilization problem, many prior works have studied memory utilization and explored how to improve it in the context of cloud.
In this paper, we perform the first large-scale study of system-level memory utilization in the context of HPC systems; through seven million machine-hours of measurements across four HPC systems, we find memory underutilization in HPC systems is much more severe than in cloud. Subsequently, we also perform the first exploration of architectural techniques to improve memory utilization specifically for HPC systems. We propose exposing each compute node's currently unused memory to its CPU(s) via novel architectural support for OS. This can enable many new microarchitecture techniques that use the abundant free memory to boost microarchitecture performance transparently without requiring any user code modification or recompilation; we refer to them as Free-memory-aware Microarchitecture Techniques (FMTs). We then present a detailed example of an FMT -- Free-memory-aware Memory Replication (FMR). On average across five HPC benchmark suites, FMR provides 13% performance and 8% system-level energy improvement compared to a highly optimized baseline representative of modern memory systems. To check the performance benefits our simulation reports, we emulated FMR in a real system and found close corroboration between simulation results and real-system emulation results. The paper ends by discussing other possible FMTs and applicability to other types of systems.
|
Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3352460.3358267 | Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture |
Keywords | Field | DocType |
DRAM, HPC Systems, Memory Architecture, Memory Management, Operating Systems, Supercomputing | Dram,Computer architecture,Architecture,Supercomputer,Computer science,Parallel computing,Memory management,Emulation,Memory architecture,Microarchitecture,Cloud computing | Conference |
ISBN | Citations | PageRank |
978-1-4503-6938-1 | 5 | 0.41 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gagandeep Panwar | 1 | 5 | 0.41 |
| Da Zhang | 2 | 12 | 2.25 |
| Yihan Pang | 3 | 5 | 0.74 |
| Mai Dahshan | 4 | 5 | 0.41 |
| Nathan DeBardeleben | 5 | 490 | 31.71 |
| Binoy Ravindran | 6 | 1459 | 139.24 |
| Xun Jian | 7 | 66 | 6.08 |