Paper Info
Title
Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation
Abstract
Integrated circuit simulators reproduce the behavior and functionality of the underlying circuits. They are part of FPGA CAD flow tools and they ensure the correctness of the circuits after the various conversions and optimizations occurring in the previous stages. During this procedure a graph with dependencies across nodes is created for each circuit design. Large circuits, and thus graphs, require more time to be simulated, making a parallel approach necessary. We explore a new solution-batch-parallel simulation in which the circuit output is calculated by worker threads that process batches of input vectors. The threads traverse and calculate their assigned nodes in parallel taking into consideration the intra-node dependencies. Furthermore, a node calculation analysis is performed and used to achieve work balance across threads. We apply this technique on the open-source Odin II framework and compare it with the existing approaches. The batch-parallel simulation is compared with the two existing approaches, single-threaded and multi-threaded, under various configurations, considering the number of threads and the batch sizes. The results demonstrate performance gains against the existing approaches in the majority of the benchmarks used for specific metrics, such as simulation elapsed time.
Year
DOI
Venue
2019
10.1109/DSD.2019.00031
2019 22nd Euromicro Conference on Digital System Design (DSD)
Keywords
Field
DocType
Field Programmable Gate Array, FPGA, VTR, CAD flow, ODIN II, parallel, batch, simulation
Digital electronics,Computer science,Correctness,Parallel computing,Circuit design,Field-programmable gate array,Thread (computing),Electronic circuit,Integrated circuit,Traverse
Conference
ISBN
Citations 
PageRank 
978-1-7281-2863-4
1
0.40
References 
Authors
11
4
Name
Order
Citations
PageRank
Maria Patrou132.45
Jean-Philippe Legault2131.89
Aaron Graham310.40
Kenneth B. Kent445854.42