Name
Abstract | ||
|---|---|---|
The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs
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(and operating as a mirror circuit when
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is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TVLSI.2019.2924721 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Logic gates,Decoding,Complexity theory,Transistors,Delays,Hardware,Sorting | Inverter,Logic gate,NMOS logic,Computer science,Electronic engineering,CMOS,Decoding methods,PMOS logic,Transistor,Electronic circuit | Journal |
Volume | Issue | ISSN |
27 | 11 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jing Guo | 1 | 45 | 6.52 |
| Shanshan Liu | 2 | 5 | 4.50 |
| lei zhu | 3 | 25 | 23.09 |
| Fabrizio Lombardi | 4 | 57 | 10.81 |