Name
Abstract | ||
|---|---|---|
In this paper, an improved current mode logic (CML) latch design is proposed for high-speed on-chip applications. Transceivers use various methods in fast data transmission in wireless/wire-line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low-power CML latch-based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180-nm standard CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1002/dac.4118 | INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS |
Keywords | DocType | Volume |
current mode logic, frequency divider, high-speed latches | Journal | 33 |
Issue | ISSN | Citations |
13 | 1074-5351 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahesh Kumawat | 1 | 0 | 0.68 |
| Abhishek Kumar Upadhyay | 2 | 0 | 0.34 |
| Sanjay Sharma | 3 | 0 | 0.34 |
| Ravi Kumar | 4 | 21 | 4.89 |
| Gaurav Singh | 5 | 0 | 0.68 |
| S. K. Vishvakarma | 6 | 10 | 6.78 |