Name
Abstract | ||
|---|---|---|
When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1049/iet-cdt.2018.5202 | IET Computers & Digital Techniques |
Keywords | Field | DocType |
energy consumption,fault tolerance,genetic algorithms,low-power electronics,network routing,network topology,network-on-chip | Mesh networking,Topology,Application specific,Computer science,Network topology,Chip,Bandwidth (signal processing),Fault tolerance,Energy consumption,Genetic algorithm | Journal |
Volume | Issue | ISSN |
14 | 1 | 1751-8601 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pinar Kullu | 1 | 2 | 1.40 |
| Yilmaz Ar | 2 | 1 | 0.35 |
| Suleyman Tosun | 3 | 35 | 6.43 |
| Suat Ozdemir | 4 | 350 | 26.30 |