Name
Title | ||
|---|---|---|
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories |
Abstract | ||
|---|---|---|
The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. The situation has led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the weights (and possibly the data being operated) using only one bit. Because approximately 90% of the operations executed by CNNs and BNNs are convolutions, a significant part of the memory transfers consists of fetching the convolutional kernels. Such kernels are usually small (e.g., 3×3 operands), and particularly in BNNs redundancy is expected. Therefore, equal kernels can be mapped to the same memory addresses, requiring significantly less memory to store them. In this context, this paper presents a custom Binary Dot Product Engine (BDPE) for BNNs that exploits the features of Resistive Random-Access Memories (RRAMs). This new engine allows accelerating the execution of the inference phase of BNNs. The novel BDPE locally stores the most used binary weights and performs binary convolution using computing capabilities enabled by the RRAMs. The system-level gem5 architectural simulator was used together with a C-based ML framework to evaluate the system’s performance and obtain power results. Results show that this novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area, when integrated with a 28 nm Fully Depleted Silicon On Insulator ARMv8 in-order core, in comparison to a fully-optimized baseline of YoloV3 XNOR-Net running in a unmodified Central Processing Unit. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSI-SoC.2019.8920343 | 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
Machine Learning,Edge Devices,Binary Neural Networks,RRAM-based Binary Dot Product Engine | Efficient energy use,Resistive touchscreen,Computer science,Binary neural network,Electronic engineering,Edge device | Conference |
ISSN | ISBN | Citations |
2324-8432 | 978-1-7281-3916-6 | 0 |
PageRank | References | Authors |
0.34 | 10 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joao Vieira | 1 | 0 | 0.34 |
| Edouard Giacomin | 2 | 6 | 4.23 |
| Yasir Mahmood Qureshi | 3 | 8 | 2.33 |
| Marina Zapater Sancho | 4 | 0 | 0.34 |
| Xifan Tang | 5 | 0 | 0.68 |
| Shahar Kvatinsky | 6 | 278 | 28.19 |
| David Atienza Alonso | 7 | 0 | 1.01 |
| Pierre-Emmanuel Gaillardon | 8 | 355 | 55.32 |