Name
Title | ||
|---|---|---|
A Hybrid Pipelined Architecture for High Performance Top-<italic>K</italic> Sorting on FPGA |
Abstract | ||
|---|---|---|
We present a hybrid pipelined sorting architecture capable of finding and producing as its output the K largest elements from an input sequence. The architecture consists of a bitonic sorter and L cascaded sorting units. The sorting unit is designed to output P elements during every cycle with the aim of increasing the throughput and lowering the latency. The function of the bitonic sorter is to generate a segmented ordered sequence. The sorting unit processes this sequence to identify and output the P largest elements. Hence, the K=PL largest elements are obtained after the segmented ordered sequence proceeds through L cascaded sorting units. Variable-length and continuous sequences are supported by the proposed sorting architecture. The results of the implementation show that the sorting architecture can achieve a throughput of 22.88 GB/s with P=16 on a state-of-the-art Field Programmable Gate Array (FPGA). |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSII.2019.2938892 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Field programmable gate array (FPGA),sorting architecture,high throughput,low latency | Journal | 67 |
Issue | ISSN | Citations |
8 | 1549-7747 | 1 |
PageRank | References | Authors |
0.35 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weijie Chen | 1 | 49 | 18.02 |
| Weijun Li | 2 | 1 | 1.37 |
| Feng Yu | 3 | 36 | 10.95 |