Name
Abstract | ||
|---|---|---|
SRAM based FPGAs (field programmable gate arrays) are volatile devices, and need to reload its configuration (bitstream) every time after power up. Bitstream compression is one of the major method to reduce the cost of storing the configuration storage and speed up configuration. However, existing complete bitstream (as compared to partial bitstream) compression methods require an external decompresser implemented either in another FPGA or CPU. This drawback prevents deployment of bitstream compression to already in-field systems. This paper drew inspiration from self-extracting archive, and utilizes the self partial reconfiguration capabilities of modern FPGAs to create a self-decompressing FPGA bitstreams so that the decompression engine is located inside the compressed bitstream itself. Analysis showed that this method will never increase the size of bitstream, and can achieve configuration time reduction whenever the compression ratio is smaller than 7/9 and the configuration reduction scales almost linearly with the compression ratio. Furthermore, the paper shows that by using bitstream assembly techniques, it is possible to choose the compression algorithm after building the target bitstream, therefore, the best compression ratio can be achieved given a pool of available decompression engines. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/MWSCAS.2019.8885346 | 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) |
Keywords | DocType | ISSN |
field programmable gate arrays,configuration compression,decompression hardware,reconfigurable logic,configuration datastreams | Conference | 1548-3746 |
ISBN | Citations | PageRank |
978-1-7281-2789-7 | 1 | 0.35 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shenghou Ma | 1 | 1 | 1.37 |
| Paul Ampadu | 2 | 1 | 1.03 |