Name
Abstract | ||
|---|---|---|
Problems of real-time hardware logic control systems design on the FPGA are considered. The control algorithm is implemented based on a timed FSM model, represented by a temporal state diagram. The design of the control device model using hardware description language VHDL in the form of the three-process pattern is made. The functional verification of the model was carried out using Active-HDL tools, the synthesis of the circuit was carried out on the Spartan 3E FPGA technology platform using Xilinx ISE CAD tools. The hardware costs for the circuit implementation of the control device were analyzed. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/EWDTS.2019.8884387 | 2019 IEEE East-West Design & Test Symposium (EWDTS) |
Keywords | Field | DocType |
timed FSM,temporal state diagram,VHDL,functional verification,pattern,FPGA | Logic Control,Functional verification,Computer science,Systems design,Field-programmable gate array,Electronic engineering,Temporal logic,VHDL,Control system,Hardware description language,Embedded system | Conference |
ISSN | ISBN | Citations |
2373-826X | 978-1-7281-1004-2 | 0 |
PageRank | References | Authors |
0.34 | 2 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maryna Miroschnyk | 1 | 0 | 0.34 |
| Olexander Shkil | 2 | 0 | 0.34 |
| Elvira Kulak | 3 | 0 | 0.34 |
| Dariia Rakhlis | 4 | 0 | 0.34 |
| Inna Filippenko | 5 | 0 | 0.34 |
| Maksym Hoha | 6 | 0 | 0.34 |
| Mykyta Malakhov | 7 | 0 | 0.34 |
| Vladyslav Sergienko | 8 | 0 | 0.34 |