Name
Title | ||
|---|---|---|
The CEDARtools Platform – Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns |
Abstract | ||
|---|---|---|
This demo showcases the ZUSPRL302 platform that was developed as the hardware vehicle enabling the work of the EU-funded H2020 Project COEMS (https://www.coems.eu/). This platform features an extensive amount of large and fast external reduced-latency RLDRAM modules, which mitigate the critical memory access times of pointer-chasing algorithms. We demonstrate that this platform enables the online reconstruction of the control flow of an application running on a standard off-the-shelf processor monitored via its execution trace interface. This reconstruction has to traverse the prepped control flow graph of the application on the basis of minimal highly-compressed execution trace data and does so at the pace of the processor for the purpose of coverage monitoring and integrity checking. The ZUSPRL302 platform is valuable contribution to the FPGA community as it enables the FPGA acceleration of fine-grained pointer chasing algorithms, which have traditionally been considered a misfit for this domain. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/FPL.2019.00079 | 2019 29th International Conference on Field Programmable Logic and Applications (FPL) |
Keywords | Field | DocType |
RLDRAM,random-memory access,Zynq-UltraScale+,VPX,random-transaction-rate,RTR | Pointer (computer programming),Control flow graph,Computer science,Control flow,Field-programmable gate array,Real-time computing,Latency (engineering),Embedded system,Traverse,Auxiliary memory,Random access | Conference |
ISSN | ISBN | Citations |
1946-147X | 978-1-7281-4885-4 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Preußer | 1 | 0 | 0.68 |
| Alexander Weiss | 2 | 27 | 3.77 |