Paper Info
Title
Approximate computing using frequency upscaling
Abstract
This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.
Year
DOI
Venue
2019
10.1049/iet-cds.2018.5422
IET Circuits, Devices & Systems
Keywords
Field
DocType
discrete cosine transforms,logic design,adders,approximation theory,digital arithmetic
Peak signal-to-noise ratio,Adder,Control theory,Discrete cosine transform,Algorithm,Image quality,Mean squared error,Throughput,Electronic circuit,Subtraction,Mathematics
Journal
Volume
Issue
ISSN
13
7
1751-858X
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Junqi Huang100.34
T. Nandha Kumar24710.94
Haider Abbas339143.88
Fabrizio Lombardi41985259.25