Name
Title | ||
|---|---|---|
Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications |
Abstract | ||
|---|---|---|
Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis, forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper, for the first time, we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs, we implement a low-cost impedance randomization unit, which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ESSCIRC.2019.8902622 | ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) |
Field | DocType | ISSN |
Power analysis,Information leakage,Computer science,Internet of Things,Static random-access memory,Electronic engineering,Electrical impedance,Macro,Information sensitivity,Embedded memory,Embedded system | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-7281-1551-1 | 0 | 0.34 |
References | Authors | |
4 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Giterman | 1 | 40 | 9.55 |
| Maoz Wicentowski | 2 | 0 | 0.34 |
| Oron Chertkow | 3 | 0 | 0.34 |
| Ilan Sever | 4 | 0 | 0.34 |
| Ishai Kehati | 5 | 0 | 0.34 |
| Yoav Weizman | 6 | 3 | 4.19 |
| Osnat Keren | 7 | 106 | 20.19 |
| Alexander Fish | 8 | 123 | 21.24 |