Paper Info
Title
Body-biasing considerations with SPAD FDSOI: advantages and drawbacks
Abstract
This article focusses on Single Photon Avalanche Diodes (SPAD) integrated in CMOS UTBB FDSOI (Ultra-Thin Body and Box Fully Depleted Silicon-On-Insulator technology), as an original approach for natively 3D SPAD pixels. In parallel to the optimization of the SPAD performances, some design issues relative to body-biasing effects are discussed in this paper. The associated electronics placed on top of the SPAD is constrained: the well layer below the box must be a P-type. Thus, only regular threshold voltage NMOS and low threshold voltage PMOS transistors can be used. The SPAD avalanche events affect the electronics through body-biasing effects, which can be advantageously exploited for an indirect sensing of the SPAD activity. Two simple indirect sensing cells are then studied. Firstly, a voltage divider realized with two transistors in series (PFET and NFET operating as active resistances) is simulated and measured to demonstrate its ability to detect avalanches. Secondly, an even simpler cell is studied, as it consists of only one NMOS transistor configured as an equivalent capacitive bridge (gate and box capacitances). Finally, the advantages and drawbacks from a design point of view are addressed.
Year
DOI
Venue
2019
10.1109/ESSDERC.2019.8901825
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)
Keywords
Field
DocType
single photon avalanche diode (SPAD),CMOS,UTBB FDSOI,body-biasing,indirect sensing
NMOS logic,Electronic engineering,Capacitive sensing,CMOS,PMOS logic,Transistor,Threshold voltage,Materials science,Voltage divider,Biasing
Conference
ISSN
ISBN
Citations 
1930-8876
978-1-7281-1540-5
0
PageRank 
References 
Authors
0.34
2
8
Name
Order
Citations
PageRank
T. Chaves de Albuquerque100.34
D. Issartel200.34
Raphael Clerc300.34
Patrick Pittet4144.13
R. Cellier500.34
W. Uhring600.34
Andreia Cathelin716834.59
Francis Calmon8207.13