Name
Abstract | ||
|---|---|---|
Advanced 28 nm node FD-SOI Z
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Experimental and 2D-TCAD results demonstrate that the memory window shifts while the retention time is reduced as the front-gate geometry is down-scaled or temperature is increased. The degradation of the memory performance can be attributed to gate tunneling current and Generation-Recombination mechanisms. The low-frequency noise and the front-gate leakage current have been experimentally studied, corroborating trap-assisted tunneling as the main degrading contributor under memory operation. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ESSDERC.2019.8901803 | ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC) |
DocType | ISSN | ISBN |
Conference | 1930-8876 | 978-1-7281-1540-5 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carlos Marquez | 1 | 0 | 0.34 |
| S. Navarro | 2 | 0 | 0.34 |
| Carlos Navarro | 3 | 0 | 0.34 |
| N. Salazar | 4 | 0 | 0.34 |
| Philippe Galy | 5 | 17 | 12.44 |
| Sorin Cristoloveanu | 6 | 3 | 6.73 |
| Francisco Gámiz | 7 | 0 | 0.34 |