Title | ||
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Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$ Root and $N^{th}$ Power Computations |
Abstract | ||
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In this paper, we propose a low complexity architecture design methodology for fixed point root and power computations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and synthesized under the
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-nm CMOS technology @ 1 GHz frequency. The synthesis results shows that the proposed
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root computation saves 19.38% on chip area and 15.86% power consumption when compared with the state of the art architecture for root computation without compromising the computational accuracy. Similarly, the proposed
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power computation saves 38% on chip area, 35.67% power consumption when compared with the state of the art power computation with out loss in accuracy. The proposed root and power computation designs save 8 clock cycle latency when compared with the state of the art implementations. |
Year | DOI | Venue |
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2019 | 10.1109/TCSI.2019.2939720 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Complexity theory,Computer architecture,Very large scale integration,Hardware,Indexes,Art | Journal | 66 |
Issue | ISSN | Citations |
12 | 1549-8328 | 3 |
PageRank | References | Authors |
0.40 | 0 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Suresh Mopuri | 1 | 12 | 2.61 |
Amit Acharyya | 2 | 139 | 31.20 |