Name
Abstract | ||
|---|---|---|
This paper presents a full digital ASK demodulation technique, targeting the usage of advanced technology nodes. Matlab simulations validate the functionality of the demodulator. The whole structure of this method uses two hysteresis comparators, one custom voltage level generator, two logical gates, a small delay block and a register. This technique allows a minimum modulation index of 3%, a SNR of 28 dB and a bitrate of fc/4. When using higher MI values, the method is more sensitive and resistant to noise, reaching for example a BER = 0.15%, with a MI = 30% and a SNR = 13 dB. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSI-SoC.2019.8920304 | 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
Amplitude shift keying (ASK) demodulator,event-based sampling,asynchronous sampling,level-crossing analogto-digital converters,adaptive level-crossing scheme,non-uniform sampling,low modulation index (MI) | Demodulation,Logic gate,Modulation index,Ask price,Comparator,Computer science,Amplitude-shift keying,Signal-to-noise ratio,Electronic engineering,Bit error rate | Conference |
ISSN | ISBN | Citations |
2324-8432 | 978-1-7281-3916-6 | 0 |
PageRank | References | Authors |
0.34 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexis Rodrigo Iga Jadue | 1 | 0 | 0.34 |
| Sylvain Engels | 2 | 0 | 0.34 |
| Laurent Fesquet | 3 | 289 | 49.04 |