Title
Non-uniform Partitioning for Collaborative Execution on Heterogeneous Architectures
Abstract
Since the demand for computing power increases, new architectures arise to obtain better performance. An important class of integrated devices is heterogeneous architectures, which join different specialized hardware into a single chip, composing a System on Chip - SoC. Within this context, effectively splitting tasks between the different architectures is primal to obtain efficiency and performance. In this work, we evaluate two heterogeneous architectures: one composed of a general-purpose CPU and a graphics processing unit (GPU) integrated into a single chip (AMD Kaveri SoC), and another composed by a general-purpose CPU and a Field Programmable Gate Array (FPGA) integrated into a single chip (Intel Arria 10 SoC). We investigate how data partitioning affects the performance of each device in a collaborative execution through the decomposition of the data domain. As a case study, we apply the technique in the well-known Lattice Boltzmann Method (LBM), analyzing the performance of five kernels in both architectures. Our experimental results show that non-uniform partitioning improves LBM kernels performance by up to 11.40% and 15.15% on AMD Kaveri and Intel Arria 10, respectively.
Year
DOI
Venue
2019
10.1109/SBAC-PAD.2019.00031
2019 31st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
Keywords
Field
DocType
Heterogeneous Architectures,Collaborative Execution,Non-Uniform Partitioning,FPGA,GPU,Lattice Boltzmann Method
System on a chip,Data domain,Computer science,Parallel computing,Lattice Boltzmann methods,Field-programmable gate array,Chip,Integrated devices,Graphics processing unit,Data partitioning
Conference
ISSN
ISBN
Citations 
1550-6533
978-1-7281-4195-4
0
PageRank 
References 
Authors
0.34
18
5
Name
Order
Citations
PageRank
Gabriel Freytag100.68
Matheus da Silva Serpa222.73
Joao Vicente Ferreira Lima300.34
Paolo Rech415523.92
Philippe O. Navaux544857.19