Name
Abstract | ||
|---|---|---|
A 1.33-Tb 4-bit/cell quadruple-level (QLC) 3-D flash memory in a 96-word-line (WL)-layer technology that achieves 8.5 Gb/mm
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has been developed. This is the biggest capacity and the highest bit density ever reported. A source-bias-negative-sense with CLK-control allows deep negative
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sensing while maintaining low supply voltage. A new two-step (8–16) programming method and VDD generator enhancement realized a narrow
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for QLC with 18% tProg improvement. Page/state-dependent word-line (WL) overdrive shortens the WL transient time by 8%. An independent plane read enables reading from different WL address from each plane in multi-plane operation. Besides, mixing selection of QLC pages (lower/middle/upper/top) in one plane and triple-level cell (TLC) pages (lower/middle/upper) or single-level cell (SLC) page in the other is also supported to provide flexibility for system implementation. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/JSSC.2019.2941758 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Programming,Generators,Couplings,Bit error rate,Reliability,Flash memories,Intellectual property | 4-bit,Flash memory,Coupling,Computer science,Voltage,Electronic engineering,Programming method,Electrical engineering,Distortion (music),Bit error rate | Journal |
Volume | Issue | ISSN |
55 | 1 | 0018-9200 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
49 | ||