Paper Info
Title
Spatial-Temporal Transformation of Matrix and Multilayer Algorithms of Binary Number Multiplication
Abstract
The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. The hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of single-digit full and half adders are investigated. Using theory of spatio-temporal graphs recursive multistep structures of the multipliers are developed. The analytical expressions for evaluation of the complexity of developed multiplier structures are obtained. It is determined that the algorithmic and conveyor structures of the multipliers have high speed and require significant hardware complexity, in contrast to the proposed multi-cycle structures that have significantly lower performance, but the hardware complexity and the corresponding occupied area on the crystal are minimal. Synthesis of developed multiplier structures on the Xilinx FPGA is performed and the convergence of theoretical and practical results of researches is shown.
Year
DOI
Venue
2019
10.1109/IDAACS.2019.8924241
2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)
Keywords
Field
DocType
matrix and multilayer multiplier,algorithm,multistep multiplier,flow and spatiak-temporal graph,FPGA
Convergence (routing),Expression (mathematics),Adder,Computer science,Matrix (mathematics),Algorithm,Field-programmable gate array,Multiplier (economics),Multiplication,Binary number
Conference
Volume
ISBN
Citations 
2
978-1-7281-4070-4
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
Volodymyr Gryga100.34
Igor Kogut200.34
Victor Holota300.34
Roman V. Kochan400.34
Stanislaw Rajba500.34
Tomasz Gancarczyk601.01
Uliana Iatsykovska700.68